The present invention relates to a semiconductor integrated circuit device which is assembled and installed in an electronic apparatus, and also concerns a manufacturing method of such a device.
Conventionally, with respect to semiconductor integrated circuit devices including semiconductor integrated circuit chips (hereinafter, referred to as IC chips), various external shapes have been proposed from the viewpoints of functions, purposes of use and assembling properties onto printed substrates of IC chips.
In recent years, particularly, in the field of small-size portable apparatuses, there has been an ever-increasing demand for further miniaturized semiconductor integrated circuit devices so as to satisfy the need of high-density assembling properties of electronic parts installed therein. Such miniaturized semiconductor integrated circuit devices are referred to as CSP (Chip Size Package or Chip Scale Package). With respect to externally connecting terminals of the CSP, solder balls, arranged in a matrix format, have been generally used.
FIG. 6(a) is a plan view that shows a structural example of a conventional semiconductor integrated circuit. FIG. 6(b) is a cross-sectional view taken along Dxe2x80x94D of FIG. 6(a). This semiconductor integrated circuit device 101 is constituted by an IC chip 102, a plurality of first electrode pads 103, a first insulating layer 104, a plurality of wires (redistribution) 105, a plurality of second electrode pads 106, a second insulation layer 107 and a plurality of externally connecting terminals 108.
A plurality of electrode pads 103 are formed on the surface of the IC chip 2. The first insulation layer 104 is stacked on the IC chip 102 in such a manner that at least one portion of each of the electrode pads 103 is exposed. The wires (redistribution) 105 are placed so as to allow the first electrode pads 103 to be electrically connected to the respective second electrode pads 106. The second insulation layer 107 is stacked on the IC chip 102 with at least one portion of the second electrode pads 106 being exposed. The externally connecting terminals 108 are formed by solder balls and placed on the respective second electrode pads 106.
The semiconductor integrated circuit device 101 having the above-mentioned structure, together with other semiconductor integrated circuit devices (CSP), has been proposed in featuring articles Part 1 and Part 2 (pages 42 to 59) of xe2x80x9cNikkei Microdevice 1998-8 (August 1 issue)xe2x80x9d published by Nikkei BP Ltd.
In accordance with this article, in the formation method of the portion corresponding to the wires 105, first, a polymer passivation film (corresponding to the first insulation layer 104) is formed, and wires are formed on this film. FIGS. 7(a) through 7(e) are drawings that show processes in which the portion of the above-mentioned wires 105 is formed by using the above-mentioned generally-used method. Here, in this state, the semiconductor integrated circuit devices 101 are formed on a wafer, and have not been divided into individual semiconductor integrated circuits.
First, a wiring base metal 109, which forms a base layer of the wires 105, is formed on the entire surface (the entire surface of the IC chip 102) of a wafer by sputtering (see FIG. 7(a)). Next, photoresist 110 is applied onto this layer (see FIG. 7(b)), and this is subjected to exposure and development so that the photoresist 110 placed on the formation area of the wiring 105 is removed (see FIG. 7(c)). Moreover, wires 105 are formed on portions from which the photoresist 110 has been removed, by plating, etc. (see FIG. 7(d)). After formation of the wires 105, all the photoresist 110 is removed, the wiring base metal 109 located between the wires 105 is etched by chemical, etc., and the second insulation layer 107 and the externally connecting terminal 108 are then formed (see FIG. 7(e)). Through these processes, the respective wires 105 are formed as an electrically isolated pattern.
Moreover, in addition to the above-mentioned formation method, another method has been proposed in which conductive paste is simply printed by using a mask formed by etching a steel plate or a meshed screen mask so as to form wires.
However, in the above-mentioned method, in an attempt to form wires (redistribution) 105 inside the conventional semiconductor circuit device by using a method having the same basic principle as a technique referred to as a photolithography method for forming fine circuits of an IC chip, the following seven processes are required.
(1) Process for forming the wiring base metal by sputtering
(2) Application of photoresist
(3) Process for exposing the photoresist
(4) Process for developing the photoresist
(5) Process for plating wiring (redistribution) material
(6) Process for removing the photoresist
(7) Process for etching the wiring (redistribution) base metal
In the above-mentioned conventional method, the above-mentioned many (seven) processes are required because of the structure in which the wires 105 are distributed on the insulation layer 104. Each of these processes requires an exclusively-used device; therefore, if there is any process that can be omitted from the above-mentioned seven processes or if there is another process that can replace any of the processes so as to reduce the production cost, without causing degradation in the functions of the wires 105, the above-mentioned seven processes will cause extra costs that would be reduced by such a process to be omitted or to be replaced with.
On the other hand, in the case when the wires 105 are formed by simply printing conductive paste by using a mask formed by etching a steel plate or a meshed screen mask, the following problems arise.
(1) A problem in which after removing the mask, the conductive paste tends to spread in the horizontal direction.
(2) A problem in which, taking into consideration the present mask processing technique (with respect to masks formed by etching steel plates, meshed screen masks, etc.), it is difficult to form wires not more than 50 xcexcm in a stable manner (without contact between the adjacent wires, without discontinuity in the wires).
In the semiconductor integrated circuit device 101, a plurality of the wires 105 are arranged so as to pass between the externally connecting terminals 108; therefore, it is not possible to narrow the distance between the externally connecting terminals 108 without the fine processing. Consequently, in the case when such a method is used, it is inevitable to design the semiconductor integrated circuit device 101 to have a large size.
Japanese Laid-Open Patent Application No. 264932/1996 xe2x80x9cTokukaihei 8-264932 (published on Oct. 11, 1996)xe2x80x9d has disclosed a formation method of solder bumps in which, at the time of forming solder bumps, solder is not transferred so that it is possible to prevent degradation in forming the solder balls (see FIGS. 8(a) through 8(e)).
In other words, in accordance with the method disclosed in the above-mentioned patent publication, prior to the printing process, a spacers 112 is placed on a printed wiring board 111, and then affixed thereon (see FIG. 8(a)) Further, the metal mask 113 is fitted to spacer 112 (see FIG. 8(b)). Then, paste 114 is put on the metal mask 113, and the solder paste 114 is filled in opening sections 116, and printed therein (see FIG. 8(b)), by using a normal screen printing method while a stage 115 being shifted from right to left as shown by arrow P (see FIG. 8(b)). Next, the metal mask 113 is removed from the spacer 112, and heated by using a reflow device (see FIG. 8(c)). Then, the solder paste 114 is allowed to form a spherical shape through surface tension (see FIG. 8(d)). In this state, this is cooled and the spacer 112 is removed from the printed wiring board 111 so that solder bumps 117 are formed on the printed wiring board 111.
The application of the above-mentioned method makes it possible to prevent solid components in flux in the solder paste from contacting during the reflow process, thereby reducing the area of wiring pads. Therefore, even when much solder paste is used, it is possible to prevent degradation in the formation of the solder bumps due to transfer of paste.
However, the technique, disclosed by the above-mentioned Patent Publication, is exclusively used for the formation of solder bumps, and if this was applied to the formation of wires (redistribution), a spacer having a thickness of not more than 10 xcexcm would be required. As in the case of the above-mentioned problem (2), it is extremely difficult to form such a thin spacer. Therefore, since the technique of the above-mentioned Patent Publication is related to a formation method of solder balls, it would raise various problems to apply this method, as it is, as the formation of wires.
An objective of the present invention is to provide a semiconductor integrated circuit device to which a fine wire processing technique is applied while maintaining the same functions as conventional devices at low costs, and a manufacturing method for such a device.
In order to achieve the above-mentioned objective, the semiconductor integrated circuit device of the present invention is provided with: a semiconductor integrated circuit chip; a first electrode formed on the circuit formation face side of the semiconductor integrated circuit chip; a first insulation layer which is stacked on the circuit formation face of the semiconductor integrated circuit chip so as to allow at least one portion on the first electrode to be exposed through an opening section; a second electrode used for external connection; a wire placed on the first insulation layer with one end being connected to the first electrode through the opening section of the first insulation layer and the other end being connected to the electrode, and a second insulation layer which is made from a material having a photosensitive property, and placed on the first insulation layer, with an opening section for allowing at least one portion of the first electrode, the wire and at least one portion of the second electrode to be exposed, and is characterized in that the wire and the second electrode are formed by filling the opening section of the second insulation layer with particles of a conductive material.
With the above-mentioned arrangement, the second insulation layer has the opening section through which the particles of the conductive material are filled at the time of formation of the wire and the second electrode, thereby serving as a mask at the time of the formation of the wire and the second electrode. The second insulation layer, which functions as a mask in this manner, serves as an insulation film for preventing the adjacent wires from contacting each other, after completion of the device; therefore, different from a mask used in a generally-used printing method, it is not necessary to remove the second insulation film is even after the filling process of the conductive particles. Moreover, since the second insulation layer is made from the material having a photosensitive property, it is allowed to function as photoresist at the time when, for example, a pattern is formed through a photolithography technique. Therefore, in the case when the pattern of the second insulation layer is formed by using the photolithography technique, it is possible to omit the process for providing photoresist in a separated manner.
In contrast, as shown as the conventional technique in the present specification, in the case of the semiconductor integrated circuit device in which the base layer wiring metal is formed by using the photolithography technique, and the wire and the second electrode are then formed through the plating process, many formation processes for the wire and the second electrode are required.
Moreover, as described above, in the present invention, it is not necessary to remove the second insulation layer after the particles of the conductive material have been filled. Therefore, different from the semiconductor integrated circuit device shown as the conventional technique in the specification, which is formed by using a method for simply applying conductive paste through a printing method, the arrangement of the present invention is free from a problem in which the conductive paste spreads in the horizontal direction after the mask has been removed. Moreover, the pattern of the second insulation layer, which functions as a mask in the present invention, is formed by using, for example, a photolithography technique that enable fine processing. Therefore, it is possible to obtain finer wires as compared with the device formed by using the conventional method.
As described above, the arrangement of the present invention makes it possible to provide a small-size semiconductor integrated circuit device which has fine wires and also provides the same functions as conventional devices at low costs.
Moreover, in order to achieve the above-mentioned objective, a manufacturing method of a semiconductor integrated circuit device in accordance with the present invention comprises: a first step of forming a first insulation layer which is formed on the circuit formation face of the semiconductor integrated circuit chip with an opening section through which at least one portion on the first electrode is exposed; a second step of forming an insulation film having a photosensitive property on the first insulation layer; a third step of forming a second insulation layer, with an opening section for allowing at least one portion of the first electrode, the wire connected to the first electrode and a formation area of the second electrode to be exposed, by exposing and developing the insulation film; and a fourth step of forming the wire and the second electrode by filling the opening section formed in the second insulation layer with particles of a conductive material.
In accordance with the above-mentioned method, since the material of the second insulation layer has a photosensitive property, the second insulation layer itself is allowed to function as photoresist. Therefore, upon patterning the second insulation layer by using a photolithography technique, it is possible to omit the process for providing photoresist in a separate manner. Consequently, the second electrode and the wire are formed through the following four processes: (1) a process for forming an insulation film used for the second insulation layer; (2) a process for exposing the insulation film; (3) a process for developing the insulation film; and (4) a process for filling a conductive material used for forming the second electrode and the wire.
In this manner, as compared with the semiconductor integrated circuit device in which the base layer wiring metal is formed by using the photolithography technique, and the wire portion is then formed through the plating process, as shown as the conventional technique in the present specification, it is possible to reduce the number of processes for forming the wire portion. Therefore, it becomes possible to manufacture a small-size semiconductor integrated circuit device at low costs.
Moreover, in the above-mentioned method, prior to forming the second electrode and the wire, the second insulation layer is preliminarily formed on the areas of the second electrode pad and the wire as well as on the area on the first electrode pad except for at least one portion. The second insulation layer functions as a mask at the time when the conductive material is filled. However, different from a mask used in a conventional printing method, since the second insulation layer is allowed to function as an insulating film for preventing contact between the adjacent wires after completion of the device, it is not necessary to remove it. Therefore, different from the semiconductor integrated circuit device shown as the conventional technique in the specification, which is formed by using a method for simply applying conductive paste through a printing method, the arrangement of the present invention is free from a problem in which the conductive paste spreads in the horizontal direction after the mask has been removed. Moreover, the pattern of the second insulation layer, which functions as a mask in the present invention, is formed by using a photolithography technique that enable fine processing. Consequently, it is possible to obtain finer wires as compared with the device formed by using the conventional method.
As described above, the application of the method of the present invention makes it possible to manufacture a small-size semiconductor integrated circuit device to which a fine wire processing technique is applied while maintaining the same functions as conventional devices at low costs.
For a fuller understanding of the nature and advantages of the invention, reference should be made to the ensuing detailed description taken in conjunction with the accompanying drawings.